 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Ordering number : ENN*6302 CMOS IC LC35256FM, FT-55U/70U 256K (32768 words x 8 bits) SRAM Control Pins: OE and CE Preliminary Overview The LC35256FM and LC35256FT are asynchronous silicon-gate CMOS SRAMs with a 32K-word by 8-bit structure. These are full-CMOS devices with 6 transistors per memory cell, and feature low-voltage operation, a low operating current drain, and an ultralow standby current. Control inputs include OE for fast memory access and CE (chip enable) for power saving and device selection. This makes these devices optimal for systems that require low power or battery backup, and makes memory expansion easy. The ultralow standby current allows these devices to be used with capacitor backup as well. Package Dimensions unit: mm 3187A-SOP28D [LC35256FM] 28 15 0.15 1 18.0 14 * Supply voltage range: 4.5 to 5.5 V * Access time at 5 V operation: LC35256FM, FT-55U: 55 ns (maximum) LC35256FM, FT-70U: 70 ns (maximum) * Standby current: 3.0 A (Ta 70C) 5.0 A (Ta 85C) * Operating temperature: -40 to +85C * Data retention voltage: 2.0 to 5.5 V * All I/O levels: TTL compatible * Input/output shared function pins, 3-state output pins * No clock required * Package 28-pin SOP (450 mil) plastic package: LC35256FM 28-pin TSOP (8 x 13.4 mm) plastic package: LC35256FT 0.4 1.27 0.1 2.3 Features SANYO: SOP28D unit: mm 3221-TSOP28 (Type I) [LC35256FT] 21 8 11.8 1.27max 22 28 1 0.55 8.1 7 0.2 0.125 0.08 SANYO: TSOP28 (Type I) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 52600RM (OT) No. 6302-1/7 0.5 13.4 1.0 11.8 9.8 8.4 LC35256FM, FT-55U/70U Pin Assignment (Top view) TSOP28 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A14 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O1 11 I/O2 12 I/O3 13 GND 14 SOP28D 28 VCC 27 WE 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O8 18 I/O7 17 I/O6 16 I/O5 15 I/O4 LC35256FT LC35256FM Block Diagram A6 A7 Address buffer Row decoder A8 A9 A10 A11 A12 A13 A14 Memory cell array 512 x 512 VCC GND Input data buffer I/O8 Input data control circuit I/O1 Column I/O circuit Column decoder Output data buffer Address buffer A0 A1 A2 A3 A4 A5 CE WE OE No. 6302-2/7 LC35256FM, FT-55U/70U Pin Functions A0 to A14 WE OE CE I/O1 to I/O8 VCC, GND Address input Read/write control input Output enable input Chip enable input Data I/O Power supply, ground Function Table Mode Read cycle Write cycle Output disable Unselected CE L L L H OE L X H X WE H L H X I/O Data output Data input High impedance High impedance Supply current ICCA ICCA ICCA ICCS Specifications Absolute Maximum Ratings Parameter Maximum supply voltage Input pin voltage I/O pin voltage Operating temperature Storage temperature Symbol VCC max VIN VI/O Topr Tstg Conditions Ratings 7.0 -0.3* to VCC + 0.3 -0.3 to VCC + 0.3 -40 to +85 -55 to +125 Unit V V V C C Note: * The minimum value is -3.0 V for pulse widths under 30 ns. I/O Capacitances at Ta = 25C, f = 1 MHz Parameter I/O pin capacitance Input pin capacitance Symbol CI/O CI VI/O = 0 V VIN = 0 V Conditions Ratings min typ 6 6 max 10 10 Unit pF pF Note: All units are not tested; only samples are tested. DC Allowable Operating Ranges at Ta = -40 to +85C, VCC = 4.5 to 5.5 V Parameter Supply voltage Input voltage Symbol VCC VIH VIL Conditions Ratings min 4.5 2.2 -0.3* typ 5.0 max 5.5 VCC + 0.3 +0.8 Unit V V V Note: * The minimum value is -3.0 V for pulse widths under 30 ns. No. 6302-3/7 LC35256FM, FT-55U/70U DC Electrical Characteristics at Ta = -40 to +85C, VCC = 4.5 to 5.5 V Parameter Input leakage current Output leakage current Output high-level voltage Output low-level voltage Symbol ILI ILO VOH VOL ICCA2 Operating current drain TTL inputs ICCA3 VIN = 0 to VCC VCE = VIH or VOE = VIH or VWE = VIL, VI/O = 0 to VCC IOH = -1.0 mA IOL = 2.0 mA VCE = VIL, II/O = 0 mA, VIN = VIH or VIL VCE = VIL, VIN = VIH Min. LC35256FM, FT-55U cycle LC35256FM, FT-70U or VIL, II/O = 0 mA, Duty 100 % 1 s cycle Ta 25C Standby mode current drain TTL inputs ICCS2 VCC - 0.2 V/ 0.2 V inputs ICCS1 VCE VCC - 0.2 V, VIN = 0 to VCC Ta 60C Ta 70C Ta 85C VCE = VIH, VIN = 0 to VCC 40 35 3.5 0.05 1.5 3.0 5.0 1.0 mA A Conditions Ratings min -1.0 -1.0 2.4 0.4 5.0 45 40 6.0 mA typ* max +1.0 +1.0 Unit A A V V mA Note: * Reference values when VCC = 5 V and Ta = 25C. AC Electrical Characteristics at Ta = -40 to +85C, VCC = 4.5 to 5.5 V AC test conditions Input pulse voltage levels: VIH = 2.4 V, VIL = 0.6 V Input rise and fall times: 5 ns Input and output timing levels: 1.5 V Output load: 30 pF + 1 TTL gate (including the jig capacitance) Read Cycle LC35256FM, FT Parameter Symbol min Read cycle time Address access time CE access time OE access time Output hold time CE output enable time OE output enable time CE output disable time OE output disable time tRC tAA tCA tOA tOH tCOE tOOE tCOD tOOD 10 5 5 20 20 55 55 55 30 10 10 5 30 25 -55U max min 70 70 70 35 -70U max ns ns ns ns ns ns ns ns ns Unit Write Cycle LC35256FM, FT Parameter Symbol min Write cycle time Address setup time Write pulse width CE setup time Write recovery time CE write recovery time Data setup time Data hold time CE data hold time WE output enable time WE output disable time tWC tAS tWP tCW tWR tWR1 tDS tDH tDH1 tWOE tWOD 55 0 40 50 0 0 25 0 0 5 20 -55U max min 70 0 50 60 0 0 30 0 0 5 30 -70U max ns ns ns ns ns ns ns ns ns ns ns Unit No. 6302-4/7 LC35256FM, FT-55U/70U Timing Charts [Read cycle] *1 tRC A0 to A14 tAA tCA CE tCOE tOA OE tOOE *5 DOUT1 to DOUT8 tOOD tCOD tOH Output data valid [Write cycle 1] (WE write) *6 tWC A0 to A14 tCW *4 CE tAS tWP *3 tWR WE tWOD *5 DOUT1 to DOUT8 tDS DIN1 to DIN8 *2 Data in stable tDH *2 tWOE *7 [Write cycle 2] (CE write) *6 tWC A0 to A14 tAS CE tWR1 tCW *4 tWP *3 WE *5 DOUT1 to DOUT8 High impedance tDS DIN1 to DIN8 tDH1 Data in stable No. 6302-5/7 LC35256FM, FT-55U/70U Notes:1. WE must be held at the high level during the read cycle. 2. Do not apply reverse phase signals to the DOUT pins when those pins are in the output state. 3. The time tWP is the period when both CE and WE are low. It is defined as the time from the fall of WE to the rise of CE or WE, whichever occurs first. 4. The time tCW is the period when both CE and WE are low. It is defined as the time from the fall of CE to the rise of CE or WE, whichever occurs first. 5. The DOUT pins will be in the high-impedance state if any one of the following hold: OE is at the high level, CE is at the high level, or WE is at the low level. 6. The OE pin must be either held high or held low during the write cycle. 7. DOUT has the same phase as the write data during this write cycle. Circuit Design Notes When designing application circuits, always take the following into consideration and design the circuits so that the absolute maximum ratings are never exceeded. * Supply voltage fluctuations * Sample-to-sample variations in the electrical characteristics of the electronic components used, including semiconductor devices, resistors, and capacitors. * Ambient temperature * Variations in the input and clock signals * The application of abnormal pulses Furthermore, be sure to operate this device within the stipulated ranges of all parameters for which an allowable operating range is specified. When CMOS IC input pins are left in the open state, through currents may occur in internal circuits to which intermediate voltage levels are applied, and this can result in incorrect circuit operation. Be sure to handle all unused input pins as specified in the device documentation. Data Retention Conditions at Ta = -40 to +85C Parameter Data retention supply voltage Symbol VDR VCE VCC - 0.2 V Ta 25C Data retention supply current ICCDR VCC = 3.0 V VCE VCC - 0.2 V Ta 60C Ta 70C Ta 85C Chip enable setup time Chip enable hold time Note: * Reference values for VCC = 3 V, Ta = 25C. ** tRC: Read cycle time tCDR tR 0 tRC** Conditions min 2.0 0.02 1.0 2.0 3.5 ns ns A typ* max 5.5 Unit V Data Retention Waveforms tCDR VCC VCCL* VIH VDR VCE GND Note: * VCCL 5 V operation: 4.5 V VCE VCC - 0.2 V Data retention mode tR No. 6302-6/7 LC35256FM, FT-55U/70U Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 2000. Specifications and information herein are subject to change without notice. PS No. 6302-7/7 |
Price & Availability of LC35256FM
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |